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· H32
RISC CPU with variable clock
·
4Mbyte local SRAM, 512 Kbyte EEPROM, 96 Kbytes trace/fault log
NVRAM, 12 Mbyte dual ported global SRAM
·
Backplane can be configured as RH32 Bus, Module Bus or VME Bus
·RS-232,
IEEE-488, IEEE 1149.1 Mil-STD 1553B and Ethernet interfaces
· Bus
history recorder, hardware trap, and fault log capability
·
Real-time debug control
·
Single or Multiple processor architecture
·
Fully supported by major software toolset vendors |
· Low
cost concept evaluation, architecture studies and system
validation
·Software
development and debug before and after flight hardware
availability
·
Configurable as functional equivalent unit for RH32 flight
systems
·
Flight computer test station
·
Single or multiple processor architecture
·
Fully supported by major software toolset vendors
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